Digital Subsystem |
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Configuration | Dynamic digital hybrid channels: 224 multiplexed (1:16) Dynamic digital: 32 Static digital: 64, TTL, bidirectional FPGA digital: 96 |
Dynamic Digital Subsystem |
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Configuration | 6U PXI format, (8) 32 channel DIO cards, (1) 16 channel DIO card |
Number of Channels | 224 hybrid, programmable drive / sense range, 50 MHz vector rate (max) |
Test Modes | Dynamic or static |
Data Output Formats (per channel) | Drive Hi, Drive Lo, Hi-Z Formatted Data: No return, Return to 1, Return to 0, Return to Hi-Z, Return to complement, Surround by complement; selectable on a per channel basis |
Drive Data Timing (per channel) | Data assert / de-assert based on Phases 1-4 |
Timing Set Options | 256 Timing Set groups with 4 Phases, 4 Windows, and 4K sequence steps 1K Timing Sets with 4 Phases, 4 Windows, and 1K sequence steps (one timing set for each sequence step) 4K Timing Sets with 1 Phase, 1 Window, and 4K sequence steps (one timing set for each sequence step) |
Phase Programming Range (Assert/ Return) | 0 ns to 64 us (using the 500 MHz master clock) |
Window Programming Range (Open/Close) | 0 ns to 64 us (using the 500 MHz master clock) |
Phase and Window Timing Resolution | 1 ns, using the 500 MHz master clock |
Capture Modes (per channel) | Mask Opening edge of Window Closing edge of Window Window – data is valid for entire window duration |
Drive/Expect Mode | Output: Drive Hi, Drive Lo, Hi-Z Expect: 1, 0, OK, between states, or mask Keep last Toggle last Accumulate CRC-16 |
Error Address Record | Record address for memory errors 1K deep error memory |
Maximum Drive Level Range | -14 V to +26 V |
Drive Voltage Level Range | Min: 0.5 V p-p Max: 26 V p-p |
Drive Voltage Accuracy | ± 25 mv, < 26 V p-p drive voltage |
Maximum Sense Level Range | -16 V to +22 V |
Sense Voltage Resolution | 16 bits |
Pull-Up/Pull-Down Current Source/Sink | ± 24 ma, programmable on a per channel basis V commutate: -16 to +22 V., programmable on a per channel basis |
Pull-Up/Pull-Down Current Source/Sink Accuracy | ± 250 uA |
Pull-Up/Pull-Down Current Source/Sink Resolution | 16 bits |
Trigger/Clock Signals | (4) Aux signals for external triggering, clocking of digital subsystem, accessible via the receiver interface and the IIP |
Static Digital Subsystem |
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Configuration | 3U PXI digital I/O card |
Number of Channels & Capabilities | 64 TTL, I/O configurable on a byte-wise basis, 24 mA source / sink |
FPGA Digital Subsystem |
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Configuration | 3U PXI card, QTY 2 |
Number of Digital Channels & Capabilities | 96 digital channels, configurable on a per pin basis. Supports TTL, LVTTL, 1.2 / 2.5 / 3.3 volt logic, 5 volt compatible, ± 4 mA 16 digital channels, configurable on a per pin basis. |
FPGA | Altera Stratix III, EP3SL50F780 C3N |
Analog Channels | 8 DE input, 8 output, 200 KS/s A/D; 1 MS/s D/A , ± 10 V input |
Switching Subsystem |
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Chassis | GX7016, 20 slot, 6U PXI switching chassis with integrated Scout receiver |
Input Switch Card | GX6032 Switch Card Configuration: 32 X16 Inputs: 32 to 128 (4 switch cards) |
LF Switch Card | GX6256 Switch Card Configuration: 16 X16 Matrix with 2 to 1 selector, (16) 2:16 multiplexers Inputs: 16 internal analog bus and 16 digital Outputs: 256 Maximum of 16 cards (4096 channels) per system |
HF Switch Card | GX6192 Switch Card Configuration: 16 X 16 matrix with (16) 1:12 multiplexers Inputs: 16 external analog inputs or 16 internal analog bus Outputs: 192 Maximum of 4 cards (768 channels) per system |
Switching System Voltage and Current Capability | 150 VDC or AC peak 1 A carry 0.5 A switching |
LF Analog Matrix Bandwidth | 20 MHz minimum (30 MHz typical), 3 dB, min., instrument port to receiver interface, 50 ohm termination |
Switching System DC Path Resistance | 6 ohms max, instrument port to receiver interface |
High Frequency (HF) Matrix Bandwidth | 100 MHz minimum (150MHz typical), 3 dB min., instrument port to HF receiver pin interface |
LF Switched Instrument Ports | DMM SMU (4) Spare (4, 4W) Spare (6) |
LF Switched Trigger Resources (32) | DMM SMU (4) CTM Oscilloscope ARB 1553 Dynamic digital subsystem FPGA Spare (8) via IIP |
HF Switched Resources (16) | DSO CTM ARB Spare (4) via IIP |
User Power |
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Number of Channels/ Type of User Power Supplies | 6, Agilent N6702 mainframe, each supply configured with disconnect relays and reversing relays |
Configuration | 0-150V, 2A (2) 0-35V, 8.5A (10) |
Analog Instrumentation |
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Configuration | DMM SMU (4 channel) DSO (4 channel) Counter / Timer (CTM), 2 channel ARB (2 channel) All resources can be routed to the receiver interface via the analog matrix and hybrid pin multiplexer |
DMM | Agilent 34410A, 6.5 digit, 5 wire interface via LF matrix |
SMU | Keithley 2425, 100W (4), ± 105 V, 1.05 A, interface via LF matrix |
SMU | Keithley 2425, 100W (4), ± 105 V, 1.05 A, interface via LF matrix |
Digital Oscilloscope | Agilent 9254A, 4 Ch., 2.5 GHz, interface via HF matrix |
Counter/Timer | Agilent 53220A, 2 channel, 350 MHz, interface via HF matrix |
Arbitrary Waveform Generator | Agilent 33522B, 2 channel, 350 MHz, interface via HF matrix |
MIL-STD 1553 Bus Interface |
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Configuration | Two Channel, Dual Redundant, Multi-Function (BC, RT & Monitor) MIL-STD-1553A/B cPCI card with IRIG –B port |
Interface | 1553 ports are routed directly to the receiver interface via the IIP |
System Controller/Monitor |
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Processor | Dual Intel® Xeon™ E5-2620 6-Core 2.0GHz Processor |
Operating System | Microsoft® Windows® 7 Ultimate 64-bit |
System Memory | 8GB DDR3-1600/PC3-12800 ECC Registered memory |
Hard Drive | Removable 1TB SATA III 7200RPM hard drive |
Media Storage | LG BT30N Blu-Ray/DVD/CD Read/Write drive |
PCIe Slots | Three x8 PCIe 3.0 slots and three x16 PCIe 3.0 slots |
USB Ports | 8 |
Ethernet Ports | 2 |
RS-232 Port | 1 |
KVM | 8 port |
Network Switch | 32 port |
RAID Array | Configurable for Raid level 0, 1,10, 3, 5, 6. Contains (4) 500 GB hot swappable HDDs |
Keyboard | SmartCard CCID Keyboard |
Monitor | 24 inch LCD, attached to swing arm on test system |
Environmental Monitoring | (4) velocity sensors – 2 per bay (2) temperature sensors – one per bay Ethernet accessible / controlled |
Instrument Interface Panel (IIP) |
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Configuration | 43 interface ports providing access to analog and trigger system resources |
Connectors | BNC |
Instrument & Trigger Resources | 1553 Bus Coupler CTM DSO ARB DMM SMU (4 ch) Trigger (8) Spare LF (4 ch, 4 w) Spare HF (2 ch) |
Test System Receiver |
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Type | 21 slot, 6U Scout receiver |
Configuration | (14) 400 pin connector blocks for digital hybrid pins (4) 59 pin coax connector blocks for HF mux pins (1) 400 pin connector block for FPGA, 1553, misc connections (1) 59 pin power block for user power |
Mechanical / Electrical / Environmental / Compliance Specifications |
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Weight | 700 lbs, dual rack configuration |
Size (overall) | 80"H x 60"W x 50"D |
Configuration | (2) 38U racks |
Input Power | 120 / 208, 5 wire WYE configuration, 40 A / phase |
Operating Temperature | 0 °C to +50 °C |
Storage Temperature | -20 °C to +60 °C |
Relative Humidity | 90%, non-condensing |
Altitude | 30,000 ft |
Compliance/ Regulatory | NFPA 70 for Electrical Equipment ANSI Z535.4 ISO 3864 |