The Gx5280 and Gx5290 boards use a multi-step delay circuit to perform two critical functions:
1. Time-align the internal main clocks across a multi-module digital domain.
2. Adjusting the timing between the data clock (data out) and strobe clock (data in) signals on each module to ensure that valid setup and/or hold parameters are met while testing the UUT.
Domain Offset
While all modules in a digital domain use a common reference clock to maintain synchronization of the data clock and strobe clock, the alignment of theese clock edges is not guaranteed across all of the modules in the domain. The Domain Offset delay can be used to calibrate the modules in a domain so that the respective data and strobe clocks on each module are not only phase locked to each other, but are also phase aligned. The edge of each module’s master clock can be adjusted in a +/- 3nS range with 250pSec resolution, with slower edges adjusted in the negative direction, and faster edges adjusted in the positive direction, until all clock edges are aligned.
Clock and Strobe Delays
The clock and strobe delays are achieved using a two stage process. The first stage is a programmable delay generator capable of generating delays from 0.0nS to 3.0nS, with a 250pS resolution. The second stage consists of a fixed delay generator with six output taps, each offset by 4nS. A switching circuit routs the clock or strobe signal through the appropriate delay path to produce a cumulative delay of the desired value.
Delay Ranges
There is a gap between the maximum 3.0nS programmable delay in the stage one delay circuit and the minimum 4.0nS delay tap in the stage two delay circuit. These 1nS gaps are found between 3.0nS and 4.0nS, 7.0nS and 8.0nS, 11.0nS and 12.0nS, 15.0nS and 16.0nS, 19.0nS and 20.0nS and 23.0nS and 24.0nS. The second reason for the non-linearity is that there are added propagation delays introduced whenever the stage two delay circuit is included in the signal path. Because these additional delay factors are uncontrolled, each module has the potential for slight variations in the cumulative delays.
|